The present disclosure relates to semiconductor memory devices, and more particularly, to the control of a power supply for a memory cell.
The advance in miniaturization of semiconductor manufacturing processes has led to a serious increase in leakage current. In addition, the leakage current problem tends to be more serious due to the reduction in the threshold voltage of a transistor and the increased capacity of an on-chip memory for meeting a demand for higher speed.
The leakage current is roughly divided into a gate leakage current, a junction leakage current, a subthreshold current, etc. The gate leakage current is a current which flows from the gate electrode through the gate insulating film to the silicon substrate in a metal-oxide-semiconductor (MOS) transistor. The junction leakage current is a current which flows from the drain electrode to the substrate. The subthreshold current is a current which flows between the drain electrode and the source electrode when the MOS transistor is off.
There are known techniques of reducing the leakage current in conventional static random access memory (SRAM) devices, such as the technique of applying a back-bias voltage to the substrate of a memory cell in the standby mode, the technique of boosting the VSS power supply to a memory cell to increase the threshold voltage of a memory cell transistor, etc. (see M. Yamaoka et al., “A 300 MHz 25 μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor,” ISSCC Dig. Tech. Papers, paper 27.2, February 2004).
In the above conventional techniques, if the voltage of the VSS power supply line is excessively boosted, data stored in a memory cell is destroyed. Therefore, in general systems, the voltage of the VSS power supply line is only allowed to increase to a level at which data of a memory cell is not destroyed, and therefore, there is a limit on the amount of the leakage current which can be blocked.